Biren Technology Hot Chips 34 presentation 'BR100 GPGPU: Accelerating Datacenter Scale AI Computing'

First-party (vendor conference) source for the Biren BR100's two interconnect figures, which had no record in this repo. Spec slide: 'Host Interface PCIe Gen5 x16 w/CXL', 'Interconnections 8 BLink', '2.3TB/s external I/O bandwidth'. Chiplet slide: '896GB/s high speed die-to-die interconnect' and 'One tapeout to empower multiple SKUs'. Server topology slide shows BR100 OAM with '550W OAM form factor with 8 cards all-to-all interconnection topology'. NOTE the slide carries its own confidentiality legend ('Confidential. This document contains confidential information of BirenTechnology'), so it is a vendor primary source but a weak one to cite for a shipping configuration. 2026-10-11: Re-read Hot Chips 34 presentation PDF (Mike Hong, Lingjie Xu). Confirmed BR100 PCIe Gen5 x16 w/ CXL, 8 BLink, 2.3TB/s external I/O, 896GB/s die-to-die interconnect, and 550W OAM 8-card topology. Raised 0.62 -> 0.70.