Biren BLink die-to-die and external I/O (BR100)

NULL - deliberately, and this is a sourcing limitation rather than a claim that the part has no interconnect. Biren's Hot Chips 34 presentation (net2-biren-hotchips-br100) gives TWO figures, neither in a usable per-link form. The spec slide reads 'Interconnections 8 BLink' and '2.3TB/s external I/O bandwidth'; the chiplet slide reads '896GB/s high speed die-to-die interconnect'. Three reasons no number is recorded: (1) the 896 GB/s is an aggregate DIE-TO-DIE figure for the two-die BR100 package, not a per-link rate, and dividing it by the link count would be this repo's invention rather than the vendor's; (2) the 2.3 TB/s external I/O figure is likewise an aggregate and carries no stated direction and no port count, so it cannot be halved or multiplied into anything meaningful; (3) the presentation carries its own confidentiality legend - 'Confidential. This document contains confidential information of BirenTechnology' - which makes it a weak citation even for the aggregates it does state. What CAN be said from the source, and is recorded in topology instead: the BR100 is '550W OAM form factor with 8 cards all-to-all interconnection topology', so the scale-up domain is 8 devices in a full mesh. To fill this record, find a Biren product datasheet or BIRENSUPA documentation stating BLink's per-link rate and direction convention.

Two distinct paths, as with several other records in this repo and easy to conflate. DIE-TO-DIE: the BR100 is a 2-die 7nm chiplet design on CoWoS packaging, the two dies joined by 896 GB/s of 'high speed die-to-die interconnect' (net2-biren-hotchips-br100) - note this is a different mechanism from BR100's four-die successor architecture, and the vendor presents the chiplet split as buying '30% more performance, 20% better yield compared with a monolithic design'. CHIP-TO-CHIP / EXTERNAL I/O: 8 'BLink' connections aggregating to 2.3 TB/s of external I/O bandwidth, with host attach over 'PCIe Gen5 x16 w/CXL' - the w/CXL suffix is worth noting as the only CXL mention in this record's source. SCALE-UP DOMAIN: the server topology slide shows BR100 OAM parts with '8 cards all-to-all interconnection topology', a direct-attached full mesh with no switch part.

None published. The BR100's server topology slide shows direct all-to-all links among the 8 OAM cards, so like amd-xgmi the domain is non-blocking within its size and there is no fabric to grow past it - a wider deployment adds nodes rather than GPUs.

Added 2026-10-03 because Biren was named as a gap in this slice's brief and had NO record at all - the interconnect slice covered NVIDIA, AMD, Huawei, Cambricon and Tenstorrent's proprietary fabrics but had nothing for Biren, which is one of the better-documented of the Chinese accelerator vendors and did publish at Hot Chips. WHAT THE VENDOR ACTUALLY PUBLISHES (Hot Chips 34, August 2022, Mike Hong / Lingjie Xu): BR100 spec slide - 'Area 1074mm^2', '2 @7nm', 'TransistorCount 77Billion', 'HostInterface PCIe Gen5 x16 w/CXL', 'PeakPerformance 2048TOPS@INT8, 1024TFLOPS@BF16, 512TFLOPS@TF32+, 256TFLOPS@FP32', 'Memory 64GB HBM2E', 'Interconnections 8 BLink', '2.3TB/s external I/O bandwidth', 'FormFactor OAM with 550W MaxTDP'; chiplet slide - '896GB/s high speed die-to-die interconnect', '30% more performance, 20% better yield compared with a monolithic design'; architecture summary - '7nm chiplet design with CoWoS packaging', '550W OAM form factor with 8 cards all-to-all interconnection topology', 'Over 300MB on-chip SRAM'. WHY EVERY RATE FIELD IS NULL, stated plainly: both published bandwidths are AGGREGATES with no per-link figure, no port count and no direction qualifier, and this repo's rule is a null plus a note rather than an invented per-link rate. The 896 GB/s die-to-die figure in particular cannot be converted into anything per-link without inventing a width, and dividing an aggregate by a link count to manufacture a per-link rate is exactly the operation that produced the ambiguity this record's sibling amd-infinity-fabric-link spent three audit passes untangling. THE DIE-TO-DIE VS CHIP-TO-CHIP DISTINCTION IS THE INTERESTING PART and is the reason the record exists separately rather than being folded into a generic 'Biren memory bus' entry: 896 GB/s of on-package die-to-die bandwidth is what makes the BR100's two dies behave as one 64 GB device rather than as a cluster, the same reasoning recorded on amd-xgmi, and it means a model can be sharded across the two dies at a fabric cost far below the part's own HBM bandwidth - whereas the 8-way all-to-all chip-to-chip mesh is a much weaker scale-up story by comparison. A reader sharding a BR100 should exhaust the intra-package split before paying for the inter-card mesh, exactly as the same argument applies on MI250X. VENDOR TRACK RECORD, which is context a reader should have: the slide carries Biren's own confidentiality legend, and the BR104 PCIe variant exists because the two-die BR100 was reportedly blocked from mass production - so treat any BR100-derived number as describing a configuration whose shipping status is uncertain. That uncertainty is another reason confidence is 0.45 and status draft. 2026-10-10: set null_bandwidth=sourcing. The record's own basis/notes already establish the reason; the field only names the case the schema now distinguishes. No number changed.