NVIDIA GeForce RTX 3090 Ti

GDDR6X 21 Gbps data rate x 384-bit / 8 = 1008 GB/s (NVIDIA Ada whitepaper, 'Memory Clock (Data Rate) 21 Gbps', 'Memory Bandwidth 1008 GB/sec')

10752 CUDA cores, 1.86 GHz boost / 1.56 GHz base, 450 W TGP, PCIe Gen4. This is the only GeForce in this set with NVLink (the 3090 family's NVLink bridge is shown on the product page), so 2-way SLI was the only consumer multi-GPU path on Ampere. Same 24 GB GDDR6X capacity as the non-Ti 3090 but a faster memory part (21 vs 19.5 Gbps => 1008 vs 936 GB/s). Batch-1 decode is memory-bound, so this bandwidth delta is the mechanical reason the Ti decodes tokens faster at identical VRAM capacity. FP8/INT8/INT4 tensor figures not recorded: not verified against a primary source in this pass. INTERCONNECT FILLED 2026-10-04: interconnect was empty; it now reads ['pcie-gen4'], from the vendor's own spec table (source the GeForce RTX 3090 family product page's 'Technology Support' row). SCALE-UP IS ABSENT AND THAT IS THE POINT: this part has no NVLink and no other GPU-to-GPU fabric, so the host link is the ONLY interconnect a multi-GPU deployment has. Do not infer a fabric from the presence of a PCIe value, and do not read the Gen number as a multi-GPU capability.