TileLang / TileKernels: a tile DSL as the middle layer between hand-written CUDA and Triton
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flops/tilelang-tile-dsl-moe-routing-quantNotes
Requirements are specific: Python 3.12+, PyTorch 2.13+, TileLang 0.1.15+, and either NVIDIA SM90/SM100 with CUDA >= 13.1 or Ascend 950 with CANN >= 9.2.0. DeepSeek ships this because FlashMLA's fused-norm-rope-attn-rope-cast kernel test depends on TileLang, TileKernels AND DeepGEMM - i.e. the modern stack is layered: DSL -> kernel library -> GEMM library. The claim 'most kernels achieve performance close to the hardware's compute or memory bandwidth limits' is DeepSeek's own and carries no numbers, so treat it as unquantified. Note also that the repo's own claim of 'dozens of highly optimized kernels' is what makes it a useful proxy for what a well-tuned tile DSL can and cannot reach.
HARDWARE-PARAMETER ROWS ADDED 2026-10-05 (schema authority pass, agent w5-schema). `affected_by_hardware` names PRODUCTS (accelerator record ids); these rows name the hardware QUANTITIES that move this class's cost, which had nowhere to live until flop.hardware_parameters was added in this commit. Every effect below is lifted verbatim from this record's own existing prose and no figure here is new - `magnitude` reproduces numbers the record already quoted. `basis` is 'unverified' where the effect was asserted with nothing concrete behind it, rather than being dressed up. The rows were pulled out of free-text notes; they are not a change to what this record claims.