NVIDIA B200
nvidia blackwell 2024
Fields
id
accelerators/nvidia-b200Vendor
nvidia
Architecture
blackwell
Release year
2024
Process (nm)
4
Form factors
oam
VRAM (GB)
180
Memory type
HBM3e
Memory bus (bit)
8,192
Memory bandwidth (GB/s)
7,700
Bandwidth basis
AUDIT CORRECTION 2026-10-04: was vram_gb 186 / 8,000 GB/s, both taken from the datasheet's GB200 NVL72 per-GPU column. Those are the wrong column for a part named B200. NVIDIA's Blackwell datasheet specification table has THREE per-GPU columns - GB200 NVL72 (186 GB / 8 TB/s), GB200 NVL4 (186 GB / 8 TB/s) and HGX B200 (180 GB / 7.7 TB/s). The HGX B200 column is the one that describes this record's part. Corroborated by AMD, whose MI355X/MI350X comparison charts quote B200 SXM 5 as '180 GB' at '7.7 TB/s' bandwidth - AMD names the figure B200 SXM5, and the datasheet's own HGX B300 column repeats 180 GB / 7.7 TB/s as the SXM-form factor lineage. The 186 GB / 8 TB/s figures are real and are correct for the GB200 rack-scale configuration; they are simply not this part's per-accelerator memory. See also the fp4/fp32/tf32/FP64 rows below, which carried the same column mix.
Peak FLOPS
precisionfp32tflops75denseyesvendor_claimyessource_idnv-blackwell-datasheetnotesAUDIT CORRECTION 2026-10-04. Was 80. NVIDIA's Blackwell datasheet HGX B200 column prints: FP4 Tensor Core 18 PFLOPS, FP8/FP6 Tensor Core 9 PFLOPS, INT8 Tensor Core 9 POPS, FP16/BF16 Tensor Core 4.5 PFLOPS, TF32 Tensor Core 2.2 PFLOPS, FP32 75 TFLOPS - all under footnote 2, 'Specifications in sparse. Dense is one-half of the sparse spec shown', except FP32 which carries footnote 1, 'Specifications in sparse | dense' (a dense|sparse pair printed left to right, single value). Dense values are therefore half the printed tensor figures: 9 / 4.5 / 4.5 / 2.25 / 1.1 PFLOPS, and FP32 75 as printed. The old value was the GB200 NVL72 column's dense figure (20/10/5/2.5 PFLOPS printed -> 10/5/5/1.25 dense, FP32 80). That column describes a rack-scale GB200 configuration, not a B200 module.basisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp32 for NVIDIA B200 (source of record: 'NVIDIA Blackwell datasheet (GB200 NVL72 / GB200 NVL4 / HGX B200)', kind: spec-sheet). Recorded dense:true as printed. Full reasoning for this row retained verbatim in notes.precisiontf32tflops1,100denseyesvendor_claimyessource_idnv-blackwell-datasheetnotesAUDIT CORRECTION 2026-10-04. Was 1250. NVIDIA's Blackwell datasheet HGX B200 column prints: FP4 Tensor Core 18 PFLOPS, FP8/FP6 Tensor Core 9 PFLOPS, INT8 Tensor Core 9 POPS, FP16/BF16 Tensor Core 4.5 PFLOPS, TF32 Tensor Core 2.2 PFLOPS, FP32 75 TFLOPS - all under footnote 2, 'Specifications in sparse. Dense is one-half of the sparse spec shown', except FP32 which carries footnote 1, 'Specifications in sparse | dense' (a dense|sparse pair printed left to right, single value). Dense values are therefore half the printed tensor figures: 9 / 4.5 / 4.5 / 2.25 / 1.1 PFLOPS, and FP32 75 as printed. The old value was the GB200 NVL72 column's dense figure (20/10/5/2.5 PFLOPS printed -> 10/5/5/1.25 dense, FP32 80). That column describes a rack-scale GB200 configuration, not a B200 module.basisvendor-spec-sheetbasis_detailTranscribed from the vendor's own tf32 for NVIDIA B200 (source of record: 'NVIDIA Blackwell datasheet (GB200 NVL72 / GB200 NVL4 / HGX B200)', kind: spec-sheet). Recorded dense:true as printed. Full reasoning for this row retained verbatim in notes.precisionbf16tflops2,250denseyesvendor_claimyessource_idnv-blackwell-datasheetnotesAUDIT CORRECTION 2026-10-04. Was 2500. NVIDIA's Blackwell datasheet HGX B200 column prints: FP4 Tensor Core 18 PFLOPS, FP8/FP6 Tensor Core 9 PFLOPS, INT8 Tensor Core 9 POPS, FP16/BF16 Tensor Core 4.5 PFLOPS, TF32 Tensor Core 2.2 PFLOPS, FP32 75 TFLOPS - all under footnote 2, 'Specifications in sparse. Dense is one-half of the sparse spec shown', except FP32 which carries footnote 1, 'Specifications in sparse | dense' (a dense|sparse pair printed left to right, single value). Dense values are therefore half the printed tensor figures: 9 / 4.5 / 4.5 / 2.25 / 1.1 PFLOPS, and FP32 75 as printed. The old value was the GB200 NVL72 column's dense figure (20/10/5/2.5 PFLOPS printed -> 10/5/5/1.25 dense, FP32 80). That column describes a rack-scale GB200 configuration, not a B200 module.basisvendor-spec-sheetbasis_detailTranscribed from the vendor's own bf16 for NVIDIA B200 (source of record: 'NVIDIA Blackwell datasheet (GB200 NVL72 / GB200 NVL4 / HGX B200)', kind: spec-sheet). Recorded dense:true as printed. Full reasoning for this row retained verbatim in notes.precisionfp16tflops2,250denseyesvendor_claimyessource_idnv-blackwell-datasheetnotesAUDIT CORRECTION 2026-10-04. Was 2500. NVIDIA's Blackwell datasheet HGX B200 column prints: FP4 Tensor Core 18 PFLOPS, FP8/FP6 Tensor Core 9 PFLOPS, INT8 Tensor Core 9 POPS, FP16/BF16 Tensor Core 4.5 PFLOPS, TF32 Tensor Core 2.2 PFLOPS, FP32 75 TFLOPS - all under footnote 2, 'Specifications in sparse. Dense is one-half of the sparse spec shown', except FP32 which carries footnote 1, 'Specifications in sparse | dense' (a dense|sparse pair printed left to right, single value). Dense values are therefore half the printed tensor figures: 9 / 4.5 / 4.5 / 2.25 / 1.1 PFLOPS, and FP32 75 as printed. The old value was the GB200 NVL72 column's dense figure (20/10/5/2.5 PFLOPS printed -> 10/5/5/1.25 dense, FP32 80). That column describes a rack-scale GB200 configuration, not a B200 module.basisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp16 for NVIDIA B200 (source of record: 'NVIDIA Blackwell datasheet (GB200 NVL72 / GB200 NVL4 / HGX B200)', kind: spec-sheet). Recorded dense:true as printed. Full reasoning for this row retained verbatim in notes.precisionfp8tflops4,500denseyesvendor_claimyessource_idnv-blackwell-datasheetnotesAUDIT CORRECTION 2026-10-04. Was 5000. NVIDIA's Blackwell datasheet HGX B200 column prints: FP4 Tensor Core 18 PFLOPS, FP8/FP6 Tensor Core 9 PFLOPS, INT8 Tensor Core 9 POPS, FP16/BF16 Tensor Core 4.5 PFLOPS, TF32 Tensor Core 2.2 PFLOPS, FP32 75 TFLOPS - all under footnote 2, 'Specifications in sparse. Dense is one-half of the sparse spec shown', except FP32 which carries footnote 1, 'Specifications in sparse | dense' (a dense|sparse pair printed left to right, single value). Dense values are therefore half the printed tensor figures: 9 / 4.5 / 4.5 / 2.25 / 1.1 PFLOPS, and FP32 75 as printed. The old value was the GB200 NVL72 column's dense figure (20/10/5/2.5 PFLOPS printed -> 10/5/5/1.25 dense, FP32 80). That column describes a rack-scale GB200 configuration, not a B200 module.basisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp8 for NVIDIA B200 (source of record: 'NVIDIA Blackwell datasheet (GB200 NVL72 / GB200 NVL4 / HGX B200)', kind: spec-sheet). Recorded dense:true as printed. Full reasoning for this row retained verbatim in notes.precisionfp6tflops4,500denseyesvendor_claimyessource_idnv-blackwell-datasheetnotesAUDIT CORRECTION 2026-10-04. Was 5000. NVIDIA's Blackwell datasheet HGX B200 column prints: FP4 Tensor Core 18 PFLOPS, FP8/FP6 Tensor Core 9 PFLOPS, INT8 Tensor Core 9 POPS, FP16/BF16 Tensor Core 4.5 PFLOPS, TF32 Tensor Core 2.2 PFLOPS, FP32 75 TFLOPS - all under footnote 2, 'Specifications in sparse. Dense is one-half of the sparse spec shown', except FP32 which carries footnote 1, 'Specifications in sparse | dense' (a dense|sparse pair printed left to right, single value). Dense values are therefore half the printed tensor figures: 9 / 4.5 / 4.5 / 2.25 / 1.1 PFLOPS, and FP32 75 as printed. The old value was the GB200 NVL72 column's dense figure (20/10/5/2.5 PFLOPS printed -> 10/5/5/1.25 dense, FP32 80). That column describes a rack-scale GB200 configuration, not a B200 module.basisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp6 for NVIDIA B200 (source of record: 'NVIDIA Blackwell datasheet (GB200 NVL72 / GB200 NVL4 / HGX B200)', kind: spec-sheet). Recorded dense:true as printed. Full reasoning for this row retained verbatim in notes.precisionint8tflops4,500denseyesvendor_claimyessource_idnv-blackwell-datasheetnotesAUDIT CORRECTION 2026-10-04. Was 5000. NVIDIA's Blackwell datasheet HGX B200 column prints: FP4 Tensor Core 18 PFLOPS, FP8/FP6 Tensor Core 9 PFLOPS, INT8 Tensor Core 9 POPS, FP16/BF16 Tensor Core 4.5 PFLOPS, TF32 Tensor Core 2.2 PFLOPS, FP32 75 TFLOPS - all under footnote 2, 'Specifications in sparse. Dense is one-half of the sparse spec shown', except FP32 which carries footnote 1, 'Specifications in sparse | dense' (a dense|sparse pair printed left to right, single value). Dense values are therefore half the printed tensor figures: 9 / 4.5 / 4.5 / 2.25 / 1.1 PFLOPS, and FP32 75 as printed. The old value was the GB200 NVL72 column's dense figure (20/10/5/2.5 PFLOPS printed -> 10/5/5/1.25 dense, FP32 80). That column describes a rack-scale GB200 configuration, not a B200 module.basisvendor-spec-sheetbasis_detailTranscribed from the vendor's own int8 for NVIDIA B200 (source of record: 'NVIDIA Blackwell datasheet (GB200 NVL72 / GB200 NVL4 / HGX B200)', kind: spec-sheet). Recorded dense:true as printed. Full reasoning for this row retained verbatim in notes.precisionfp4tflops9,000denseyesvendor_claimyessource_idnv-blackwell-datasheetnotesAUDIT CORRECTION 2026-10-04. Was 10000. NVIDIA's Blackwell datasheet HGX B200 column prints: FP4 Tensor Core 18 PFLOPS, FP8/FP6 Tensor Core 9 PFLOPS, INT8 Tensor Core 9 POPS, FP16/BF16 Tensor Core 4.5 PFLOPS, TF32 Tensor Core 2.2 PFLOPS, FP32 75 TFLOPS - all under footnote 2, 'Specifications in sparse. Dense is one-half of the sparse spec shown', except FP32 which carries footnote 1, 'Specifications in sparse | dense' (a dense|sparse pair printed left to right, single value). Dense values are therefore half the printed tensor figures: 9 / 4.5 / 4.5 / 2.25 / 1.1 PFLOPS, and FP32 75 as printed. The old value was the GB200 NVL72 column's dense figure (20/10/5/2.5 PFLOPS printed -> 10/5/5/1.25 dense, FP32 80). That column describes a rack-scale GB200 configuration, not a B200 module.basisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp4 for NVIDIA B200 (source of record: 'NVIDIA Blackwell datasheet (GB200 NVL72 / GB200 NVL4 / HGX B200)', kind: spec-sheet). Recorded dense:true as printed. Full reasoning for this row retained verbatim in notes.
TDP (W)
1,000
Unified memory
no
Consumer part
no
notes
AUDIT CORRECTION 2026-10-04 - COLUMN-MIXING ERROR, THE SAME CLASS AS THE 9000-VS-15000 B300 FP4 ERROR. Every numeric field in this record was taken from the datasheet's GB200 NVL72 per-GPU column instead of its HGX B200 column, so the record described a rack-scale configuration while being named B200. OLD -> NEW: vram_gb 186 -> 180; memory_bandwidth_gbps 8000 -> 7700; fp32 80 -> 75; tf32 1250 -> 1100; bf16 2500 -> 2250; fp16 2500 -> 2250; fp8 5000 -> 4500; fp6 5000 -> 4500; int8 5000 -> 4500; fp4 10000 -> 9000. tdp_w 1000 was already correct - it is the HGX B200 column's 'Configurable up to 1,000W' - which is exactly why the error survived review: one field in every group was right, so the record never looked internally inconsistent. Independent corroboration for the memory correction: AMD's own MI355X/MI350X product pages plot 'B200 SXM 180GB' at 180 GB and 7.7 TB/s against the MI355X/MI350X in all three comparison charts (AI Performance, HPC Performance, Memory Capacity & Bandwidth). On the dense/sparse semantics, the record's flags and numbers are now mutually consistent AND match NVIDIA's footnotes: every Tensor Core figure on this sheet is printed SPARSE and dense is one-half (footnote 2), while FP32 carries footnote 1, 'Specifications in sparse | dense'. So a bare '20 PFLOPS FP4' quote for B200 in the wild is the GB200-column SPARSE number, and even a correctly-columned '18 PFLOPS FP4' is still sparse - dense FP4 for a B200 module is 9 PFLOPS. This is the same trap as the H100 sheet's footnote 2 'With sparsity'. The 'other' rows this schema would need for FP64/FP64 Tensor Core are absent from this record entirely: NVIDIA prints FP64/FP64 Tensor Core 37 TFLOPS for the HGX B200 column (40 TFLOPS for GB200 NVL72), and both sheets carry that row under footnote 2's sparsity note even though FP64 on Blackwell has no 2:4 sparse path in practice - treat the printed FP64 as a vendor claim with an unresolved sparsity footnote rather than assuming it is dense. AMD's MI355X page independently quotes B200 FP64 as 37 TFLOPs, matching the HGX B200 column exactly, which resolves the 40-vs-37 vendor discrepancy that nvidia-gb200-nvl72 records as contested: 37 is the B200 figure and 40 is the GB200 NVL72 figure. Source is a reseller-hosted copy of NVIDIA's PDF because NVIDIA's own resources.nvidia.com copy is a JS viewer; treat figures as vendor-claim only.
FP4 DENSE IS CONTESTED AT THE VENDOR (status set accordingly). The Blackwell datasheet's HGX B200 column prints a bare '18 PFLOPS' under footnote 2 ('Dense is one-half of the sparse spec shown'), giving dense 9, which is what this record stores. NVIDIA's own Blackwell Architecture Technical Brief prints HGX B200 as 'FP4 Tensor Core Dense/Sparse | 14/18' - dense 14. 9 vs 14 is an NVIDIA self-disagreement across two first-party documents, not an error in this repo. The datasheet reading is retained because it is internally consistent with every other tensor row in the same table. A reader should treat B200 FP4 dense as 9-14 TFLOPS pending resolution.
Notes
AUDIT CORRECTION 2026-10-04 - COLUMN-MIXING ERROR, THE SAME CLASS AS THE 9000-VS-15000 B300 FP4 ERROR. Every numeric field in this record was taken from the datasheet's GB200 NVL72 per-GPU column instead of its HGX B200 column, so the record described a rack-scale configuration while being named B200. OLD -> NEW: vram_gb 186 -> 180; memory_bandwidth_gbps 8000 -> 7700; fp32 80 -> 75; tf32 1250 -> 1100; bf16 2500 -> 2250; fp16 2500 -> 2250; fp8 5000 -> 4500; fp6 5000 -> 4500; int8 5000 -> 4500; fp4 10000 -> 9000. tdp_w 1000 was already correct - it is the HGX B200 column's 'Configurable up to 1,000W' - which is exactly why the error survived review: one field in every group was right, so the record never looked internally inconsistent. Independent corroboration for the memory correction: AMD's own MI355X/MI350X product pages plot 'B200 SXM 180GB' at 180 GB and 7.7 TB/s against the MI355X/MI350X in all three comparison charts (AI Performance, HPC Performance, Memory Capacity & Bandwidth). On the dense/sparse semantics, the record's flags and numbers are now mutually consistent AND match NVIDIA's footnotes: every Tensor Core figure on this sheet is printed SPARSE and dense is one-half (footnote 2), while FP32 carries footnote 1, 'Specifications in sparse | dense'. So a bare '20 PFLOPS FP4' quote for B200 in the wild is the GB200-column SPARSE number, and even a correctly-columned '18 PFLOPS FP4' is still sparse - dense FP4 for a B200 module is 9 PFLOPS. This is the same trap as the H100 sheet's footnote 2 'With sparsity'. The 'other' rows this schema would need for FP64/FP64 Tensor Core are absent from this record entirely: NVIDIA prints FP64/FP64 Tensor Core 37 TFLOPS for the HGX B200 column (40 TFLOPS for GB200 NVL72), and both sheets carry that row under footnote 2's sparsity note even though FP64 on Blackwell has no 2:4 sparse path in practice - treat the printed FP64 as a vendor claim with an unresolved sparsity footnote rather than assuming it is dense. AMD's MI355X page independently quotes B200 FP64 as 37 TFLOPs, matching the HGX B200 column exactly, which resolves the 40-vs-37 vendor discrepancy that nvidia-gb200-nvl72 records as contested: 37 is the B200 figure and 40 is the GB200 NVL72 figure. Source is a reseller-hosted copy of NVIDIA's PDF because NVIDIA's own resources.nvidia.com copy is a JS viewer; treat figures as vendor-claim only.
FP4 DENSE IS CONTESTED AT THE VENDOR (status set accordingly). The Blackwell datasheet's HGX B200 column prints a bare '18 PFLOPS' under footnote 2 ('Dense is one-half of the sparse spec shown'), giving dense 9, which is what this record stores. NVIDIA's own Blackwell Architecture Technical Brief prints HGX B200 as 'FP4 Tensor Core Dense/Sparse | 14/18' - dense 14. 9 vs 14 is an NVIDIA self-disagreement across two first-party documents, not an error in this repo. The datasheet reading is retained because it is internally consistent with every other tensor row in the same table. A reader should treat B200 FP4 dense as 9-14 TFLOPS pending resolution.