Peak FLOPS
precisionfp64tflops34denseyesvendor_claimyessource_idnv-h100-datasheetnotes—basisvendor-spec-sheetbasis_detailH100 datasheet SXM column, 'FP64 34 TFLOPS'. Not a tensor-core figure and not halved by the sparsity footnote - see nvidia-gb200-nvl72 for the vendor's explicit FP64 sparsity exclusion.precisionfp32tflops67denseyesvendor_claimyessource_idnv-h100-datasheetbasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp32 for NVIDIA H100 SXM (source of record: 'NVIDIA H100 Tensor Core GPU datasheet (H100 SXM / PCIe / NVL)', kind: spec-sheet). Recorded dense:true as printed.precisiontf32tflops494.5denseyesvendor_claimyessource_idnv-h100-datasheetbasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own tf32 for NVIDIA H100 SXM (source of record: 'NVIDIA H100 Tensor Core GPU datasheet (H100 SXM / PCIe / NVL)', kind: spec-sheet). Recorded dense:true as printed.precisionbf16tflops989.5denseyesvendor_claimyessource_idnv-h100-datasheetbasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own bf16 for NVIDIA H100 SXM (source of record: 'NVIDIA H100 Tensor Core GPU datasheet (H100 SXM / PCIe / NVL)', kind: spec-sheet). Recorded dense:true as printed.precisionfp16tflops989.5denseyesvendor_claimyessource_idnv-h100-datasheetbasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp16 for NVIDIA H100 SXM (source of record: 'NVIDIA H100 Tensor Core GPU datasheet (H100 SXM / PCIe / NVL)', kind: spec-sheet). Recorded dense:true as printed.precisionfp8tflops1,979denseyesvendor_claimyessource_idnv-h100-datasheetbasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp8 for NVIDIA H100 SXM (source of record: 'NVIDIA H100 Tensor Core GPU datasheet (H100 SXM / PCIe / NVL)', kind: spec-sheet). Recorded dense:true as printed.precisionint8tflops1,979denseyesvendor_claimyessource_idnv-h100-datasheetbasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own int8 for NVIDIA H100 SXM (source of record: 'NVIDIA H100 Tensor Core GPU datasheet (H100 SXM / PCIe / NVL)', kind: spec-sheet). Recorded dense:true as printed.
notes
CORRECTED 2026-10-03: no value changed; dense flags re-verified against the H100 datasheet PDF itself (source acc2-nv-h100-datasheet-2023, page-2 table footnote 2 'With sparsity'). The H100 SXM column prints TF32 989 / BFLOAT16 1,979 / FP16 1,979 / FP8 3,958 / INT8 3,958 TOPS, all SPARSE; dense is exactly half, matching the 494.5 / 989.5 / 989.5 / 1,979 / 1,979 stored here. FP64 34, FP64 Tensor 67 and FP32 67 carry no sparsity footnote and are recorded as printed. AUDIT CORRECTION: the dense/sparse flag on the tensor rows was inverted. FP16 989.5 / FP8 1979 TFLOPS are DENSE. NVIDIA prints 989 TF32 / 1,979 FP16 / 3,958 FP8 'WITH SPARITY' (sparse = 2x). These rows were previously flagged dense:false, which wrongly told a reader they were sparse. The stored numbers are correct dense values. CRITICAL: the datasheet prints 989 TFLOPS TF32 / 1,979 BFLOAT16+FP16 / 3,958 FP8+INT8, ALL MARKED 'WITH SPARITY'. The DENSE numbers recorded here are exactly half of NVIDIA's printed sparse figures (494.5 TF32 / 989.5 BF16+FP16 / 1,979 FP8+INT8). Quoting NVIDIA's printed 1,979 'FP16 TFLOPS' as a dense figure overstates real dense throughput by 2x - and note NVIDIA's own marketing copy, the AMD MI300X page footnote and the H200 spec table all label 1,979 as the WITH-SPARITY figure, so anyone reading the sheet without the footnote halves it twice. FP64 34 and FP32 67 are dense and sparsity-independent. TDP is configurable up to 700W. NVLink 900 GB/s bidirectional per GPU. The 'other' row is FP64 34 TFLOPS (dense) - this schema's precision enum has no fp64 member.