Compute Express Link 3.x

CORRECTED IN AUDIT 2026-10-03: this record had HALVED A PER-DIRECTION FIGURE, storing the bidirectional aggregate as the per-direction value and thereby understating CXL by 2x. PCI-SIG quotes PCIe-family bandwidth PER LANE PER DIRECTION - its own FAQ states 32 GT/s is '32.0 Gigabits/second/Lane/DIRECTION' and that x32 at 32.0 GT/s gives '128.0 Gigabytes/second in each direction SIMULTANEOUSLY' (net2-pcisig-pcie5-faq). CXL shares the PCIe physical layer and the same convention. CXL 3.x runs on the PCIe 6.0 physical layer: 64 GT/s PAM4 at 2 bits/symbol = 128 Gb/s raw per lane per direction, flit-mode framing at 236B/256B gives 118.0 Gb/s payload per lane per direction, x16 = 1,888 Gb/s = 236.0 GB/s PER DIRECTION, bidirectional aggregate 472 GB/s. The recorded value now equals pcie-gen6 exactly, which is correct since CXL 3.x IS the PCIe 6.0 physical layer. The consortium's 4.0 page (link-cxl-about) confirms CXL 3.x uses the 256B flit format, retained by 4.0. Recorded as one record covering 3.0 and 3.1 because no primary source distinguishing 3.1's additions was retrievable. AUDIT NOTE: the previous 60.5 was wrong by 4x rather than 2x - it was derived by halving a 121 figure that was itself half of the correct 236, so it both halved and ignored PAM4's 2 bits per symbol.

Switched fabric with memory pooling and multi-host sharing across a CXL domain; peer-to-peer device-to-device traffic is possible within the domain, which is new relative to 2.0.

A real switched fabric at this generation, and the first CXL generation where multi-level switching and fabric-managed resource allocation are in scope - the closest thing CXL has to a scale-up domain, though nothing like NVLink's coherent GPU-to-GPU rate.

Inference consequence: the useful jump from 2.0 to 3.x is topology as much as speed - pooled memory at 236 GB/s per direction x16 makes KV-cache spill and weight offload across a shared pool practical for large-batch serving where bandwidth is amortised over many requests. It is also the first CXL generation with multi-level switching and fabric-managed resource allocation, plus peer-to-peer device-to-device traffic within the domain, which is new relative to 2.0. A 3.1-specific record was not created: no primary CXL Consortium page stating what 3.1 added was retrievable, so rather than guess this record covers 3.0 and 3.1 and says so. The consortium states full backward compatibility from 4.0 to 3.x, 2.0, 1.1 and 1.0. AUDIT NOTE: the previous stored value made CXL 3.x look like a marginal step over CXL 2.0 (31.5 -> 60.5); on the corrected ladder the step is 63 -> 236, a 3.7x, which is the generation's real character and moves CXL 3.x from 'roughly PCIe 5 speed' to 'above PCIe 5 by a wide margin'.