Compute Express Link: About CXL · inference-research

Fields

id

sources/link-cxl-about

URL

https://computeexpresslink.org/about-cxl/

Publisher

CXL Consortium

Kind

spec-sheet

Accessed

2026-10-03

notes

Consortium page describing CXL 4.0: doubles bandwidth from 64 GT/s to 128 GT/s with zero added latency, retains the CXL 3.x 256B flit format, introduces native x2 width for fan-out, up to four retimers, bundled ports combining host and Type 1/2 device ports, memory RAS enhancements, and full backward compatibility with CXL 3.x, 2.0, 1.1 and 1.0.

Notes

Consortium page describing CXL 4.0: doubles bandwidth from 64 GT/s to 128 GT/s with zero added latency, retains the CXL 3.x 256B flit format, introduces native x2 width for fan-out, up to four retimers, bundled ports combining host and Type 1/2 device ports, memory RAS enhancements, and full backward compatibility with CXL 3.x, 2.0, 1.1 and 1.0.

Cross-references

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