PCI-SIG FAQ 'What bit rates does the PCIe 5.0 specification support and how does it compare to prior PCIe generations?'

THE AUTHORITATIVE SOURCE ON DIRECTIONAL CONVENTION FOR THIS ENTIRE FAMILY. States the rate ladder per generation as 'Gigabits/second/Lane/DIRECTION of raw bandwidth' (2.5 / 5.0 / 8.0 / 16.0 / 32.0 for PCIe 1.0-5.0), and gives a worked example: 'A PCIe 5.0 Link consisting of 32 Lanes and operating at a bit rate of 32.0 GT/s provides an effective raw bandwidth of 128.0 Gigabytes/second IN EACH DIRECTION SIMULTANEOUSLY' - and 32 x 32 / 8 = 128.0, which proves the figure is PER DIRECTION and not a bidirectional aggregate. This resolves the three-times-repeated halving error on pcie-gen4, pcie-gen5 and the whole cxl-* family in this repo. Read this before comparing any PCIe or CXL number to an NVIDIA or AMD fabric number.