Compute Express Link 4.0

CORRECTED IN AUDIT 2026-10-03: this record had HALVED A PER-DIRECTION FIGURE, storing the bidirectional aggregate as the per-direction value and thereby understating CXL by 2x. PCI-SIG quotes PCIe-family bandwidth PER LANE PER DIRECTION - its own FAQ states 32 GT/s is '32.0 Gigabits/second/Lane/DIRECTION' and that x32 at 32.0 GT/s gives '128.0 Gigabytes/second in each direction SIMULTANEOUSLY' (net2-pcisig-pcie5-faq). CXL shares the PCIe physical layer and the same convention. The consortium states CXL 4.0 'Doubles the bandwidth to 128GTs with zero added latency' (link-cxl-about). 128 GT/s PAM4 at 2 bits/symbol = 256 Gb/s raw per lane per direction, flit framing at 236B/256B gives 236.0 Gb/s payload per lane per direction, x16 = 3,776 Gb/s = 472.0 GB/s PER DIRECTION, bidirectional aggregate 944 GB/s. The recorded value is now exactly 2x cxl-3-x, the clean generational relationship the consortium's 'doubles the bandwidth' claim requires. The consortium also adds 'zero added latency' for the doubling, retains the 256B flit format, introduces native x2 width, implements bundled ports combining host and Type 1/2 device ports, and supports up to four retimers for channel reach. AUDIT NOTE: the old value of 121 was the bidirectional aggregate, and the old notes claimed this left CXL 'roughly 4x below NVLink 4'. At the corrected 472 per direction, CXL 4.0 is essentially AT PARITY with NVLink 4's 450 GB/s per direction per GPU, which materially changes this record's recommendation.

Switched fabric with pooling, now with native x2 width for platform fan-out, bundled ports combining host and Type 1/2 accelerator ports, and support for up to four retimers for channel reach.

Mature switched fabric. Bundled ports are the notable feature for accelerators: combining a host port with Type 1/2 device ports raises the bandwidth of one connection, which is how an accelerator-attached tier would get beyond a single x16 worth of bandwidth.

Inference consequence: at 472 GB/s per direction x16 this is the first CXL generation whose per-direction rate matches NVLink 4 (450 GB/s per direction per GPU on H100), and with bundled ports and native x2 widths an accelerator-attached CXL tier could exceed it. That still does not make CXL a tensor-parallel fabric: CXL's coherent model is CPU-memory-centric and it has no in-network reduction, so TP collectives over CXL pay full latency with no SHARP equivalent. The credible use is memory expansion and pooling - large-batch decode with KV cache resident in pooled CXL memory, where bandwidth is amortised over many concurrent requests rather than paid per token. Four retimers of channel reach matters for rack-scale placement. Consortium states full backward compatibility with 3.x, 2.0, 1.1, 1.0. AUDIT NOTE: this correction changes the practical guidance in this file. The previous version concluded CXL was 'the first generation within ~4x of NVLink 4' and therefore still far off TP fabric class; the corrected figure puts raw per-direction rate at parity, so the remaining objections to CXL for collectives are architectural (no in-network reduction, CPU-centric coherence) rather than bandwidth, and the memory-tier case is stronger than the old record implied.