PCI-SIG FAQ, category 'PCI Express - 6.0' (bit rate, PAM4 rationale, Flit Mode, FEC)

RETRIEVED AND TRANSCRIBED VERBATIM 2026-10-05. THE AUTHORITATIVE SOURCE FOR THE DIRECTION WORDING OF PCIe 6.0, and it settles a contradiction that had propagated into data/interconnect/pcie-gen6.json. On direction, verbatim, from the question 'What is the bit rate for the PCIe 6.0 specification?': - 'The PCIe 6.0 specification supports a data rate of 64.0 GT/s and up to 256.0 GB/s via a x16 configuration, while providing low latency, minimal complexity and reduced bandwidth overhead. PCIe 6.0 technology delivers a doubling of the 32.0 GT/s and 128.0 GB/s bit rate of the PCIe 5.0 specification.' And from 'Why does PCIe 6.0 specification utilize PAM4 signaling over NRZ signaling?', which is the decisive sentence because it uses the direction word EXPLICITLY: - 'The utilization of PAM4 allows the PCIe 6.0 specification to reach 64.0 GT/s data rate and up to 256.0 GB/s BIDIRECTIONAL bandwidth via a x16 configuration.' So PCI-SIG labels 256.0 GB/s at x16 as BIDIRECTIONAL. The per-direction figure is therefore 128.0 GB/s, and the arithmetic confirms it exactly: 16 lanes x 64 GT/s / 8 = 128.0 GB/s per direction, x2 for both directions = 256.0. The same 128.0 GB/s also appears one question earlier as the PCIe 5.0 figure - which is coherent, because PCIe 5.0 at 32 GT/s x16 is 64.0 GB/s raw per direction and 128.0 GB/s raw bidirectional. PCI-SIG is quoting RAW (unencoded) bandwidth throughout this FAQ. On why GT/s and GB/s diverge from Gen 5 onward, verbatim: - 'NRZ uses two levels of signaling, while PAM4 uses four levels. It packs two bits of information into the same amount of time on a serial channel.' - 'With the 64 GT/s data rate enabled by PAM4 encoding in the PCIe 6.0 specification, the bit error rate (BER) was several orders of magnitude higher than the 10-12 BER in all prior generations.' - 'Flit Mode supports the higher BER expected in PAM4 (10-6 vs 10-12 in NRZ).' - 'PCI-SIG adopted a 256-Byte Flit structure, which includes the variable-sized Transaction Layer Packets (TLPs) and Data Link Layer Payloads (DLLPs). This is a necessary change due to the move to PAM4 encoding and Forward Error Correction (FEC), which only works on fixed-size data packets. Flit Mode is required for 64.0 GT/s PAM4 and is supported at all Link speeds.' NOTE WHAT IS NOT PUBLISHED HERE: PCI-SIG does not state the flit framing efficiency as a ratio (it never writes '242B/256B' on this page), so the 242/256 payload efficiency used to derive the 121.0 GB/s per-direction payload figure is NOT from this source. PCI-SIG publishes the raw rate only here. The 242/256 figure comes from w7p-wikipedia-pcie-link-performance. Marked on pcie-gen6 accordingly.