PCI Express 7.0

WHY BANDWIDTH JUMPS NON-LINEARLY VERSUS GT/s - THE POINT A GT/s-ONLY COMPARISON GETS WRONG, stated because it is this repo's second recurring error mode after the direction convention. From PCIe 5.0 to PCIe 6.0 the GT/s rate doubles (32 -> 64) and the RAW bidirectional figure doubles with it (128 -> 256 GB/s), but the PAYLOAD per direction goes 63.0 -> 121.0 GB/s, a ratio of 1.92x, NOT 2x. The missing 4% is the encoding change: PCIe 1.0-5.0 use NRZ with 128b/130b line coding (98.46% efficiency), whereas PCIe 6.0 and 7.0 use PAM4 with 242B/256B flit framing (94.53% efficiency). PAM4 carries two bits per symbol instead of one - PCI-SIG, verbatim: 'NRZ uses two levels of signaling, while PAM4 uses four levels. It packs two bits of information into the same amount of time on a serial channel' (w7p-pcisig-pcie6-faq). A reader who compares Gen5 to Gen6 by GT/s alone would compute 32 -> 64 and conclude 'exactly double', then find the real payload is 1.92x and conclude one of the records is wrong. Both are right; the framing overhead is real and is the entire discrepancy. The corollary in the other direction: Gen6 -> Gen7 IS exactly 2.00x on payload per direction (121.0 -> 242.0) because the framing is unchanged between them - so PAM4 makes the FIRST post-NRZ step non-linear and every subsequent step linear again, and any table of this family that shows a uniform 2x per generation is either quoting raw rates or has silently mixed conventions. SECOND COST OF PAM4, from the same PCI-SIG FAQ, verbatim: 'the bit error rate (BER) was several orders of magnitude higher than the 10-12 BER in all prior generations' and 'Flit Mode supports the higher BER expected in PAM4 (10-6 vs 10-12 in NRZ)' - so Gen6/Gen7 require FEC and CRC, and are a materially different signal-integrity and retimer problem from Gen5. INFERENCE CONSEQUENCE: at 242.0 GB/s per direction, PCIe 7.0 x16 finally exceeds NVLink 4's 450 GB/s per direction... note that it does NOT - it remains roughly 1.9x below it, the same ratio as Gen6, because PCIe and NVLink are on different ladders. What PCIe 7.0 does change is that a tensor-parallel group over a PCIe host attach becomes far less absurd than at Gen5: PCIe 7.0 is the first generation where the host link is no longer the dominant bottleneck for weight streaming on a large model. Deployment reality check, because a spec release is not silicon: PCI-SIG's own framing of the generation is future-facing, and Ian Cutress (More Than Moore) is quoted as saying 'Datacenters are ready to start deploying networks built on PCIe 7.0 technology' - intent, not shipments. No accelerator in data/accelerators/ in this repo is recorded as attaching over PCIe 7.0, so this record is a spec-generation fact with no measured consumer yet. Revision currency: PCIe 7.0 reached FINAL specification on 11 June 2025 (w7p-pcisig-pcie7-release-pr), so it is published, but per the same release 'Pathfinding for the PCIe 8.0 specification is already in progress' at 256.0 GT/s.