AMD Instinct MI250
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accelerators/amd-instinct-mi250Notes
AUDIT 2026-10-03 (AMD convention check, no value changed): AMD's Instinct product pages print a 'Peak X Performance' row (DENSE) and a separate 'Peak X Performance with Structured Sparsity' row (SPARSE, exactly 2x the dense value) only from the CDNA3/MI300 generation onward. The CDNA2 pages for MI250 print NO structured-sparsity variant for any precision - only 'Peak Half Precision (FP16)', 'Peak INT4', 'Peak INT8' and 'Peak bfloat16' - so every dense flag on this record is correct under AMD's own labelling. Concretely, on these pages AMD prints FP16 == INT8 == INT4 == BF16 at the same number (181.0 on the MI210, 362.1 on the MI250, 383.0 on the MI250X), all dense and all equal. That the four precisions are numerically identical is the CDNA2 property, not a sparsity artifact: unlike CDNA4 (MI350), CDNA2 has no 2:4 structured-sparsity path to double anything. IMPORTANT: despite having HALF the compute of the MI250X, the MI250 has the SAME 128 GB of memory and the same 3.2 TB/s. That is counter-intuitive and worth stating plainly, because it inverts the usual capacity/compute trade-off.
AMD's spec table: MI250 = 208 CUs / 13,312 SPs; MI250X = 220 CUs / 14,080 SPs. Ratio 208/220 = 0.945, and 362.1/383 = 0.945 - the compute is exactly proportional to CU count.
But both SKUs ship 128 GB HBM2e on an 8192-bit interface at 3.2 TB/s. Per the MI300X datasheet and AMD's CDNA2 documentation, a CDNA2 GCD carries 64 GB; the MI250 is the single-GCD cut-down. If it is one GCD, how does it have 128 GB? AMD's published MI250 figures say 128 GB / 8192-bit / 3.2 TB/s regardless. Two readings are possible and AMD does not resolve them on this page: (a) the MI250 OAM is still a 2-GCD package with more CUs fused off for yield, keeping the full 128 GB memory and bandwidth; or (b) the SKU is memory-rich by design. Either way the actionable fact for a reader is that memory is NOT halved - do not assume 64 GB.
This is a CONTESTED point about the physical die count that I could not resolve from AMD's own product pages; recording it rather than guessing. What is not contested: the memory figures, the CU counts, and the flops, all straight from AMD's spec table.
Same generation limits as the MI250X: no TF32, no FP8, no structured sparsity. All entries dense-only. Vector/matrix FP32 split (45.3 vector / 90.5 matrix) is preserved as two entries.
500W TDP / 560W peak, passive OAM, PCIe 4.0 x16, 8 Infinity Fabric links at 100 GB/s. ROCm LLVM target gfx90a.