inference/research
verifiedhigh · 0.95updated 2026-10-03

Google Cloud TPU v4

google v4 2021

Fields

id
accelerators/google-tpu-v4
Vendor
google
Architecture
v4
Release year
2021
Process (nm)
7
Form factors
custom
VRAM (GB)
32
Memory type
hbm2
Memory bandwidth (GB/s)
1,200
Bandwidth basis
Vendor-published per-chip HBM2 bandwidth of 1200 GBps; bus width not stated, so it cannot be derived from bit width.
Peak FLOPS
precisionbf16tflops275denseyesvendor_claimyessource_idasic-tpu-v4-specsbasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own bf16 for Google Cloud TPU v4 (source of record: 'Cloud TPU v4 system architecture', kind: spec-sheet). Recorded dense:true as printed.precisionint8tflops275denseyesvendor_claimyessource_idasic-tpu-v4-specsbasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own int8 for Google Cloud TPU v4 (source of record: 'Cloud TPU v4 system architecture', kind: spec-sheet). Recorded dense:true as printed.
TDP (W)
192
Unified memory
yes
Consumer part
no
notes
Per-chip figures; one pod is 4096 chips at 1.1 EFLOPS BF16/INT8. 275 TFLOPS is the shared bf16-or-int8 peak (the docs state '275 teraflops (bf16 or int8)', i.e. INT8 is NOT 2x BF16 here, unlike the v5/v6 line). TDP 192 W is the documented measured maximum; min/mean are 90/170 W. Memory hierarchy: two TensorCores per chip share one unified 32 GiB HBM2 space, with an on-chip Cmem SRAM feed tier that the v4 paper describes. That SRAM feed tier is the reason v4 decode is not simply DRAM-bound: Google added 8-bit mode support and faster MXU weight-loading specifically to allow lower batch sizes. Interconnect is ICI over 3D mesh, reconfigurable into a torus, with optical circuit switches between cubes. MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). The vendor publishes no memory-bus width for this part, and none was back-computed from the published bandwidth. This is the correct state of the field for a part with no vendor width figure.

Notes

Per-chip figures; one pod is 4096 chips at 1.1 EFLOPS BF16/INT8. 275 TFLOPS is the shared bf16-or-int8 peak (the docs state '275 teraflops (bf16 or int8)', i.e. INT8 is NOT 2x BF16 here, unlike the v5/v6 line). TDP 192 W is the documented measured maximum; min/mean are 90/170 W. Memory hierarchy: two TensorCores per chip share one unified 32 GiB HBM2 space, with an on-chip Cmem SRAM feed tier that the v4 paper describes. That SRAM feed tier is the reason v4 decode is not simply DRAM-bound: Google added 8-bit mode support and faster MXU weight-loading specifically to allow lower batch sizes. Interconnect is ICI over 3D mesh, reconfigurable into a torus, with optical circuit switches between cubes. MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). The vendor publishes no memory-bus width for this part, and none was back-computed from the published bandwidth. This is the correct state of the field for a part with no vendor width figure.

Cross-references

Interconnect (1)