PCI-SIG FAQ 'What bit rates does the PCIe 5.0 specification support and how does it compare to prior PCIe generations?' - re-retrieved verbatim 2026-10-05 as the convention anchor for PCIe 1.0-5.0

RE-RETRIEVED AND TRANSCRIBED VERBATIM 2026-10-05. This is the same page as the existing source net2-pcisig-pcie5-faq; a second source id is NOT being claimed for it. It is registered here only because this worker's records (pcie-gen1, pcie-gen2, pcie-gen7) cite generations 1.0, 2.0 and 7.0, which net2-pcisig-pcie5-faq's text does not reach - 1.0 and 2.0 appear only as ladder entries, and 7.0 does not appear at all. Same URL, same publisher, same publication; the distinguishing content is the re-verification date and the explicit ladder transcription below. VERBATIM, in full, the part this repo depends on: - 'A PCIe Link consists of 1, 2, 4, 8, 12, 16, or 32 Lanes, all operating at one of the supported signaling rates.' - 'PCIe 1.0 provided an effective 2.5 Gigabits/second/Lane/direction of raw bandwidth.' - 'PCIe 2.0 added support for 5.0 Gigabits/second/Lane/direction of raw bandwidth.' - 'PCIe 3.0 added support for 8.0 Gigabits/second/Lane/direction of raw bandwidth.' - 'PCIe 4.0 added support for 16.0 Gigabits/second/Lane/direction of raw bandwidth.' - 'PCIe 5.0 adds support for 32.0 Gigabits/second/Lane/direction of raw bandwidth.' - 'A PCIe 5.0 Link consisting of 32 Lanes and operating at a bit rate of 32.0 GT/s provides an effective raw bandwidth of 128.0 Gigabytes/second in each direction simultaneously.' WHY THIS PAGE SETTLES THE DIRECTION CONVENTION, stated once so no record has to re-derive it: the ladder is written per LANE PER DIRECTION ('Gigabits/second/Lane/direction'), and the worked example's arithmetic closes on that reading - 32 lanes x 32.0 Gb/s / 8 = 128.0 GB/s, with no factor of two anywhere, while the sentence says 'in each direction'. A bidirectional aggregate reading would need 32 lanes x 2 directions x 32 / 8 = 256 GB/s, which is not the number PCI-SIG prints. So the figure is per direction, and because a PCIe lane is dual-simplex (separate TX and RX conductor pairs), a per-direction figure at a given lane count is already the whole number for that direction - it must NOT be halved again. The 32-lane example is not a special case: at x16 the same reading gives 64.0 GB/s per direction raw, and 128.0 GB/s bidirectional aggregate, which is why '128 GB/s' appears in this repo as Gaudi 3's aggregate host figure and never as a per-direction one. LANE COUNTS PUBLISHED BY PCI-SIG: 1, 2, 4, 8, 12, 16, 32. Note 12 and 32 are real PCIe widths; the x16 convention used across data/interconnect/pcie-gen*.json is a choice for comparability, not the maximum width. PCIe 6.0 and 7.0 share the physical layer with CXL 4.0 / CXL 5.0 respectively and, per w7p-pcisig-pcie6-faq, 'Flit Mode ... is supported at all Link speeds'. NOT ESTABLISHED BY THIS PAGE: any encoding or framing scheme. PCI-SIG never names 8b/10b, 128b/130b or 242B/256B here, so this page fixes the DIRECTION and the RAW rates for gens 1-5 and nothing about payload efficiency. For encoding, cite w7p-wikipedia-pcie-link-performance.