Wikipedia: PCI Express - 'Comparison table' (PCI Express link performance) plus the PCIe 1.0a / 2.0 encoding paragraphs

SECONDARY source. Read against the primary PCI-SIG pages because it is the only source in this set that publishes the ENCODING EFFICIENCY per generation, which is what converts a GT/s rate into a payload GB/s figure. Used here ONLY for (a) the line-code and framing scheme per generation and (b) the payload-vs-raw efficiency. Every GT/s rate it states is independently corroborated by PCI-SIG's own pages in this repo. VERBATIM encoding and rate rows from the 'PCI Express link performance' table (Version | Year | Line code | encoding | Transfer rate per lane | Throughput GB/s at x1/x2/x4/x8/x16): - '1.0 | 2003 | NRZ | 8b/10b | 2.5 GT/s | 0.25 | 0.5 | 1 | 2 | 4' - '2.0 | 2007 | [line code inherited] | [encoding inherited] | 5.0 GT/s | 0.5 | 1 | 2 | 4 | 8' - '3.0 | 2010 | 128b/130b | 8.0 GT/s | 0.985 | 1.969 | 3.938 | 7.877 | 15.754' - '4.0 | 2017 | 16.0 GT/s | 1.969 | 3.938 | 7.877 | 15.754 | 31.508' - '5.0 | 2019 | 32.0 GT/s | 3.938 | 7.877 | 15.754 | 31.508 | 63.015' - '6.0 | 2022 (first implemented 2025) | PAM-4, FEC | 1b/1b, 242B/256B FLIT | 64.0 GT/s | 7.563 | 15.125 | 30.25 | 60.5 | 121' - '7.0 | 2025 (specification released) | 128.0 GT/s | 15.125 | 30.25 | 60.5 | 121 | 242' - '8.0 | 2028 (planned) | 256.0 GT/s | 30.25 | 60.5 | 121 | 242 | 484' THE THREE TABLE FOOTNOTES ARE THE DIRECTION CONVENTION, verbatim, and they are unusually explicit for a secondary source: - 'In each direction (each lane is a dual simplex channel).' - attached to both the transfer-rate and throughput column headers. - 'Transfer rate refers to the encoded serial bit rate; 2.5 GT/s means 2.5 Gbit/s serial data rate.' - 'Throughput indicates the usable bandwidth (i.e. only including the payload, not the 8b/10b, 128b/130b, or 242B/256B encoding overhead). The PCIe 1.0 transfer rate of 2.5 GT/s per lane means a 2.5 Gbit/s serial bit rate; after applying a 8b/10b encoding, this corresponds to a useful throughput of 2.0 Gbit/s = 250 MB/s.' So this table's throughput column is PAYLOAD PER DIRECTION per lane, and its x16 column is payload per direction at x16. Every figure in it was reproduced exactly by 'GT/s x encoding_efficiency / 8 x 16' with no further halving, which is the check that confirms the convention. On the generations Wikipedia does not tabulate a line code for, verbatim: 'PCIe 1.x uses an 8b/10b encoding scheme, resulting in a 20% (= 2/10) overhead on the raw channel bandwidth' and 'Like 1.x, PCIe 2.0 uses an 8b/10b encoding scheme, therefore delivering, per-lane, an effective 4 Gbit/s max. transfer rate from its 5 GT/s raw data rate.' This is the citation for 8b/10b on BOTH Gen1 and Gen2 - the table only prints it on the Gen1 row, so a reader comparing rows would otherwise wrongly conclude Gen2 changed encoding. On the raw-vs-payload distinction, verbatim: 'A PCIe 1.x lane for example offers a data rate on top of the physical layer of 250 MB/s (simplex). This is due to a 2.5 GT/s bit rate multiplied by the efficiency of the 8b/10b line code ... This is not the payload bandwidth but the physical layer bandwidth - a PCIe lane has to carry additional information for full functionality.' Useful as the authority that even the per-lane post-encoding figure is NOT a payload figure. KNOWN DEFECT IN THIS SOURCE, recorded so a future reader does not inherit it: the infobox at the top of the article states 'Speed: Dual simplex, up to 242 GB/s' with no generation and no direction qualifier. 242 GB/s is the Gen7 x16 PER-DIRECTION PAYLOAD figure (correct per its own comparison table), so the infobox is an undated, unlabelled restatement of the newest generation - but presented bare it is exactly the kind of direction-free number the gotcha aa-gotcha-pcie-peak-bandwidth-direction-convention warns about. Also note the article's own PCIe 7.0 prose says 'up to 242 GB/s PER DIRECTION in x16 configuration' while the objective list it quotes from PCI-SIG says 'up to 512 GB/s bi-directionally'; those two are consistent with each other and with PCI-SIG, and 242 vs 512 is payload-vs-raw, not a contradiction - but the article presents both numbers for one generation without labelling which is which, so cite the numbers, never the article, for direction.