Memory bandwidth (GB/s)
300
Bandwidth basis
GDDR6 6.25Gbps x 384-bit = 300 GB/s. Bus width is the standard AD104 384-bit; NVIDIA's page prints only the 300 GB/s aggregate.
Peak FLOPS
precisionfp32tflops30.3denseyesvendor_claimyessource_idnv-l4-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp32 for NVIDIA L4 (source of record: 'NVIDIA L4 Tensor Core GPU product page (spec table)', kind: spec-sheet). Recorded dense:true as printed.precisiontf32tflops60denseyesvendor_claimyessource_idnv-l4-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own tf32 for NVIDIA L4 (source of record: 'NVIDIA L4 Tensor Core GPU product page (spec table)', kind: spec-sheet). Recorded dense:true as printed.precisionbf16tflops121denseyesvendor_claimyessource_idnv-l4-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own bf16 for NVIDIA L4 (source of record: 'NVIDIA L4 Tensor Core GPU product page (spec table)', kind: spec-sheet). Recorded dense:true as printed.precisionfp16tflops121denseyesvendor_claimyessource_idnv-l4-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp16 for NVIDIA L4 (source of record: 'NVIDIA L4 Tensor Core GPU product page (spec table)', kind: spec-sheet). Recorded dense:true as printed.precisionfp8tflops242.5denseyesvendor_claimyessource_idnv-l4-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp8 for NVIDIA L4 (source of record: 'NVIDIA L4 Tensor Core GPU product page (spec table)', kind: spec-sheet). Recorded dense:true as printed.precisionint8tflops242.5denseyesvendor_claimyessource_idnv-l4-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own int8 for NVIDIA L4 (source of record: 'NVIDIA L4 Tensor Core GPU product page (spec table)', kind: spec-sheet). Recorded dense:true as printed.
notes
AUDIT CORRECTION: the dense/sparse flag on the tensor rows was inverted. FP16 121 / FP8 242.5 TFLOPS are DENSE. NVIDIA L4 page prints FP16 242* / FP8 485* with '* Shown with sparsity. Specifications are one-half lower without sparsity.' These rows were previously flagged dense:false, which wrongly told a reader they were sparse. The stored numbers are correct dense values. CRITICAL: NVIDIA's L4 page prints 120 TF32 / 242 BF16+FP16 / 485 FP8+INT8 marked '*' (with sparsity); dense is half - recorded here as 60 / 121 / 242.5. L4 is the inference-first Ada part: 72W, single-slot low-profile, no NVLink, no MIG, and only 300 GB/s. At batch 1 decode it is entirely bandwidth-bound - 300 GB/s is roughly a tenth of H100 SXM, so it is a fit-many-small-models card, not a fit-one-big-model card. FP32 30.3 is dense. No 'other' row: Ada has no FP64 hardware path, so there is no FP64 figure to record.